//储存子密钥
module Memory(
	Memory_Write_Enable,
	Memory_Address,
	Memory_Write_Data,
	Memory_Read_Data,
	clk
);
	//输入
	input wire clk;
	input wire Memory_Write_Enable;
	input wire [4:1] Memory_Address;
	input wire [48:1] Memory_Write_Data;
	//输出
	output wire [48:1] Memory_Read_Data;
	//内部寄存器
	reg [48:1] RAM[15:0];
	
	assign Memory_Read_Data = RAM[Memory_Address[4:1]];
	
	always@(posedge clk) begin
		if(Memory_Write_Enable) begin
			RAM[Memory_Address[4:1]] <= Memory_Write_Data;
		end
	end


endmodule